Semiconductor memory device and production method thereof

ABSTRACT

A semiconductor memory device according to an embodiment has a memory cell array including: a plurality of lower wirings extending in the first direction; a plurality of upper wirings extending in the second direction, the upper wirings placed above the plurality of lower wirings; a plurality of memory cells provided at respective crossings of the plurality of lower wirings and the plurality of upper wirings; and an interlayer insulating film provided between the plurality of memory cells adjacent in the second direction, and the device is characterized in that the upper wiring includes: an upper firing first section deposited on the memory cell; and an upper wiring second section deposited on the interlayer insulating film, the upper wiring second section larger in crystal grain size than the upper wiring first section, and an upper surface of the memory cell is lower than an upper surface of the interlayer insulating film.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.14/021,085, filed on Sep. 9, 2013, and is based upon and claims thebenefit of priority from the prior U.S. Provisional Application61/819,014, filed on May 3, 2013, the entire contents of each of whichare incorporated herein by reference.

BACKGROUND

1. Field

Embodiments of the present invention relates to a semiconductor memorydevice and a production method of the device.

2. Description of the Related Art

As a technique for further shrinking of memory cells, resistance-changesemiconductor memory devices have been proposed in which variableresistive elements are used for memory cells. A phase-change memoryelement that a resistance value changed depending on thecrystalline/amorphous state change of a chalcogenide compound, an MRAMelement that uses changes in resistance due to a tunnelmagnetoresistance effect, a polymer ferroelectric RAM (PFRAM) memoryelement that has a resistive element formed from a conductive polymer,an ReRAM element that induces changes in resistance by applyingelectrical pulses, etc. are known as the variable resistive elements.

In the case of the semiconductor memory devices with the use of thevariable resistive elements, semiconductor memory devices can beachieved which are large in capacity and small in chip size, because thesize per memory cell can be reduced, and additionally, because thememory cell array can be three-dimensionally structured.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an example of a block diagram illustrating the configurationof a semiconductor memory device according to a first embodiment;

FIG. 2 is an example of a perspective view illustrating a portion of amemory cell array in the semiconductor memory device according to theembodiment;

FIG. 3A is an example of a cross-sectional view for one memory cell inthe semiconductor memory device according to the embodiment;

FIG. 3B is an example of an equivalent circuit schematic of the memorycell in the semiconductor memory device according to the embodiment;

FIG. 4 is an example of a diagram illustrating an example of a variableresistive element in the semiconductor memory device according to theembodiment;

FIGS. 5 to 10 are examples of perspective views illustrating, in theorder of steps, the steps of producing the memory cell array in thesemiconductor memory device according to the embodiment;

FIG. 11 is an example of a graph showing the relationship between acombination of a base material with a wiring material and the crystalgrain size of wiring;

FIG. 12 is an example of a graph showing the relationship between thewiring thickness for each base material and the sheet resistance ofwiring;

FIGS. 13, 14A, 14B, 15A and 15B are examples of cross-sectional views ofmemory cell arrays for explaining the crystal grain size of wiring inthe semiconductor memory device according to the embodiment;

FIG. 16 is an example of a graph showing the relationship between thedepth of the upper surface of a memory cell layer to the upper surfaceof an interlayer insulating film and the sheet resistance of wiring inthe semiconductor memory device according to the embodiment;

FIG. 17 is an example of a perspective view illustrating a step ofproducing a memory cell array in a semiconductor memory device accordingto a second embodiment;

FIG. 18 is an example of a perspective view illustrating another step ofproducing the memory cell array in the semiconductor memory deviceaccording to the embodiment; and

FIG. 19 is an example of a perspective view illustrating another step ofproducing the memory cell array in the semiconductor memory deviceaccording to the embodiment.

DETAILED DESCRIPTION

A semiconductor memory device according to an embodiment has, when twodirections crossing one another are referred to as a first direction anda second direction, whereas a direction crossing the first direction andthe second direction is referred to as a vertical direction, a memorycell array including: a plurality of lower wirings extending in thefirst direction; a plurality of upper wirings extending in the seconddirection, the upper wirings placed above the plurality of lowerwirings; a plurality of memory cells provided at respective crossings ofthe plurality of lower wirings and the plurality of upper wirings; andan interlayer insulating film provided between the plurality of memorycells adjacent in the second direction, and the device is characterizedin that the upper wiring includes: an upper firing first sectiondeposited on the memory cell; and an upper wiring second sectiondeposited on the interlayer insulating film, the upper wiring secondsection larger in crystal grain size than the upper wiring firstsection, and an upper surface of the memory cell is lower than an uppersurface of the interlayer insulating film.

Semiconductor memory devices and production method thereof according toembodiments will be described below with reference to the drawings.

First Embodiment

First, the general configuration of a semiconductor memory deviceaccording to a first embodiment will be described.

FIG. 1 is an example of a block diagram illustrating the configurationof the semiconductor memory device according to the present embodiment.This semiconductor memory device includes a memory cell array 1. Thememory cell array 1 includes a plurality of memory cells MC arranged ina matrix form, and a plurality of word lines WL (lower wirings) and aplurality of bit lines BL (upper wirings) for selecting the plurality ofmemory cells MC.

The memory cell array 1 has the word lines WL electrically connected toa row control circuit 3 that selects the word lines WL to make itpossible to erase data in the memory cells MC, write data in the memorycells MC, and read out data from the memory cells MC. Furthermore, thememory cell array 1 has the bit lines BL electrically connected to acolumn control circuit 2 that controls the bit lines BL to make itpossible to erase data in the memory cells MC, write data in the memorycells MC, and read out data from the memory cells MC.

Next, the structure of the memory array 1 will be described.

FIG. 2 is an example of a perspective view illustrating a portion of amemory cell array in the semiconductor memory device according to thepresent embodiment. In FIG. 2, the row direction is shown as the “Xdirection” (first direction), the column direction is shown as the “Ydirection” (second direction), and the vertical direction crossing therow direction and the column direction is shown as the “Z direction”.The same applies to the subsequent diagrams.

The memory cell array 1 includes a plurality of bit lines BL extendingin the column direction, a plurality of word lines WL extending in therow direction, and memory cells MC arranged at the respective crossingsof the plurality of bit lines BL and the plurality of word lines WL soas to be sandwiched by the both wirings. For the bit lines BL and theword lines WL, materials are desirable which are resistant to heat andlow in resistance value, and for example, W, WSi, NiSi, CoSi, and thelike can be used.

Next, the memory cells MC will be described.

FIGS. 3A and 3B are a cross-sectional view and an equivalent circuitschematic of a memory cell in the semiconductor memory device accordingto the present embodiment. FIG. 3A is an example of a cross-sectionalview for one memory cell cut along the line I-I′ in FIG. 2, and viewedin an in the direction of an arrow.

The memory cell MC is, as shown in FIG. 3B, composed of a circuit thathas a variable resistive element VR and a non-ohmic element NO connectedin series.

As the variable resistive element VR which can vary in resistance valuewith current, heat, chemical energy, or the like by applying a voltage,electrodes EL2 and EL3 are placed which function an upper barrier metaland a lower adhesive layer. Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co,Ti, TiN, TaN, LaNiO, Al, PrIrO_(x), PtRhO_(x), Rh/TaAlN, etc. are usedas the electrode materials. Further, a top electrode ELT composed of Wor the like for uniform orientation may be placed on the electrode EL3as shown in FIG. 3B, if necessary. In addition, it is also possible toinsert a buffer layer, a barrier metal layer, an adhesive layer, etc.separately in the memory cells MC.

The variable resistive element VR can use an element that has aresistance value changed depending on a phase transition between acrystalline state and an amorphous state, such as chalcogenide, anelement that has an oxide film resistance changed by changing the oxygenconcentration of the film, an element that has a resistance valuechanged by depositing metal cations to form cross-linkages (conductingbridges) between electrodes or ionizing the deposited metal to destroythe cross-linkages, and an element (ReRAM) that has a resistance valuechanged by applying a voltage or a current, etc.

FIG. 4 is a diagram illustrating an example of a ReRAM element. TheReRAM element shown in FIG. 4 has a recording layer 12 placed betweenelectrode layers 11 and 13. The recording layer 12 is composed of acomposite compound including at least two types of cationic elements. Atleast one of the cationic elements is a transition element that has a dorbital incompletely filled with electrons, and shortest distancebetween adjacent cationic elements is 0.32 nm or less. Specifically, thecomposite compound is represented by a chemical formula A_(x)M_(y)X_(z)(A and M are different elements from each other), and composed of amaterial that has crystalline structure such as, for example, a spinelstructure (AM₂O₄), an ilmenite structure (AMO₃), a delafossite structure(AMO₂), a LiMoN₂ structure (AMN₂), a wolframite structure (AMO₄), anolivine structure (A₂MO₄), a hollandite structure (A_(x)MO₂), aramsdellite structure (A_(x)MO₂), and a perovskite structure (AMO₃).

In the example of FIG. 4, A represents Zn, M represents Mn, and Xrepresents O. In the recording layer 12, a smaller white circle, alarger white circle, and a smaller black circle respectively representsa diffuse ion (Zn), an anion (O), and a transition element ion (Mn). Theinitial state of the recording layer 12 is a high-resistance state, andwhen a negative voltage is applied to the electrode layer 13 with theelectrode layer 11 at a fixed electric potential, some of diffuse ionsin the recording layer 12 move to the electrode layer 13, and the numberof diffuse ions in the recording layer 12 is decreased relatively withrespect to anions. The diffuse ions moving to the electrode layer 13receive electrons from the electrode layer 13 to deposit as metal, andthus form a metal layer 14. The excessive anions in the recording layer12 results in an increase in the valence of the transition element ionin the recording layer 12. Thus, the carrier injection provides therecording layer 12 with electron conductivity to complete the setoperation. For reproduction, a minute electric current value may beapplied to such an extent that the material constituting the recordinglayer 12 cause no change in resistance. In order to reset the programstate (low-resistance state) to the initial state (high-resistancestate), for example, a large current may be applied to the recordinglayer 12 for a sufficient period of time to carry out Joule heating, andaccelerate the redox reaction of the recording layer 12. In addition, itis also possible to carry out the reset operation by applying anelectric field reversed from that in the setting.

The non-ohmic element NO is composed of, for example, various types ofdiodes such as a Schottky diode, a PN junction diode, and a PIN diode, aMIM (Metal-Insulator-Metal) structure, a SIS structure(Silicon-Insulator-Silicon), etc. The electrodes EL1 and EL2 for forminga barrier metal layer and adhesive layer may be also inserted therein.Pt, Au, Ag, TiAlN, SrRuO, Ru, RuN, Ir, Co, Ti, TiN, TaN, LaNiO, Al,PrIrO_(x), PtRhO_(x), Rh/TaAlN, etc. are used as the electrodematerials. In addition, in the case of using a diode, unipolar operationcan be carried out in consideration of characteristics, whereas it ispossible to carry out bipolar operation in the case of a MIM structure,an SIS structure, or the like. It is to be noted that the non-ohmicelement NO and the variable resistive element VR may be arranged upsidedown with respect to FIG. 3, and the polarity of the non-ohmic elementNO may be reversed vertically.

Next, steps of producing the memory cell array 1 will be described.

FIGS. 5 to 10 are examples of perspective views illustrating, in theorder of steps, the steps of producing the memory cell array in thesemiconductor memory device according to the present embodiment.

As shown in FIG. 5, a transistor, etc. (not shown) constituting aperipheral circuit may be formed on a semiconductor substrate 101. Aninterlayer insulating layer 102 formed of SiO₂ or the like is depositedon the transistor, etc. Subsequently, CVD (Chemical Vapor Deposition),PVD (Physical Vapor Deposition), or the like is used to stack a lowerwiring layer 103′ to serve as the word line WL, a layer 104″ to serve asthe electrode EL1, a layer 105″ to serve as the non-ohmic element NO, alayer 106″ to serve as the electrode EL2, a layer 107″ to serve as thevariable resistive element VR, a layer 108″ to serve as the electrodeEL3, and a layer 109 ⁽³⁾ to serve as the top electrode ELT sequentiallyon the interlayer insulating layer 102. Among these layers, the layers104″ to 109 ⁽³⁾ serve as a memory cell layer 110 ⁽³⁾ to serve as thememory cell MC. Thereafter, if necessary, a hard mask composed of SiO₂or the like in a line/space pattern, which extends in the row direction,may be deposited on the 109 ⁽³⁾.

Subsequently, as shown in FIG. 6, for example, a dry etching method isused for the memory cell layer 110 ⁽³⁾ and the lower wiring layer 103′to form a plurality of grooves 112 (first grooves) extending in the rowdirection, until the upper surface of the interlayer insulating layer102 is exposed. This etching forms the lower wiring layer 103′ and thememory cell layer 110 ⁽³⁾ into a lower wiring layer 103 and a memorycell layer 110″ segmentalized in the row direction. Further, the lowerwiring layer 103 serves as the word line WL.

Subsequently, as shown in FIG. 7, the grooves 112 are filled with aninterlayer insulating film 113′ formed of, for example, SiO₂. The uppersurfaces of the memory cell layer 110″ and interlayer insulating film113′ are smoothed by using CMP (Chemical Mechanical Polish) or the like.Subsequently, as shown in FIG. 8, an upper portion of the layer 109′ toserve as the top electrode ELT is removed about 5 nm to 10 nm by a wetetching method. The wet etching is carried out with the use of an acidicchemical or the like so as to provide a selectivity to the interlayerinsulating film 113′. This wet etching forms the layer 109″ into a layer109′, and the memory cell layer 110′ into a memory cell layer 110′. Thisstep makes the upper surface of the layer 109′ to serve as the topelectrode ELT lower than the upper surface of the interlayer insulatingfilm 113′.

Subsequently, as shown in FIG. 9, for example, a sputtering method isused to deposit an upper wiring layer 114′ to serve as the bit line BLon the memory cell layer 110′ and the interlayer insulating film 113′.The deposited upper wiring layer 114′ herein can be, depending on thedifference in average crystal grain size, separated into a first section114 a′ (hereinafter, simply referred to as a “first section”) depositedon the memory cell layer 110′ and a second section 114 b′ (hereinafter,simply referred to as a “second section”) deposited on the interlayerinsulating film 113′. It is to be noted that the bit line BL formed fromthe upper wiring layer 114′ and the upper wiring layer 114′ will bedescribed in detail later.

Subsequently, as shown in FIG. 10, a dry etching method or the like isused for the upper wiring layer 114′, the interlayer insulating film113′, and the memory cell layer 110′ to form a plurality of grooves 115(second grooves) extending in the column direction, until the uppersurface of the lower wiring layer 103 is exposed. This dry etching formsthe upper wiring layer 114′, the interlayer insulating film 113′, andthe memory cell layer 110 into an upper wiring layers 114, an interlayerinsulating films 113, and a memory cell layers 110 separated in thecolumn direction respectively. Further, the upper wiring layer 114 andthe memory cell layer 110 respectively serve as the word line WL and thememory cell MC. It is to be noted that the bottoms of the grooves 115may be positioned at the upper surfaces of the electrode 104′ in thememory cell layer 110′.

If necessary, the grooves 115 are filled with an interlayer insulatingfilm or the like formed of SiO₂ or the like, thereby allowing the memorycell array 1 to be produced.

Next, advantageous effects will be described with reference to thememory cell array 1 produced in accordance with the steps describedabove.

First of all, properties will be described with reference to the firstsection 114 a and second section 114 b of the upper wiring layer 114(bit line BL).

FIG. 11 is a graph showing the relationship between a combination of abase material with a wiring material and the crystal grain size ofwiring. FIG. 11 shows: (i) a case of using a base of SiO₂ and a wiringof 50 nm thick W; (ii) a case of using a base of SiO₂ and 10 nm thickTiN and a wiring of 50 nm thick WN; (iii) a case of using a base of SiO₂and 10 nm thick WN and a wiring of 50 nm thick W; (iv) a case of using abase of SiO₂ and 10 nm thick TiN and a wiring of 50 nm thick W; (v) acase of using a base of SiO₂ and 10 nm thick TiN and a wiring of 50 nmthick WN; and (vi) a case of using a base of SiO₂, 10 nm thick TiN, and10 nm thick WN and a wiring of 50 nm thick W.

As is clear from this graph, regardless of the wiring material W or WN,the wirings have a relatively large average crystal grain size of 50 nmor more in the case of the bases without TiN, whereas the wirings have asmall average crystal grain size not more than the half in the case ofthe bases with TiN. In other words, the wiring resistance is lower inthe case of the bases without TiN, whereas the wiring resistance ishigher in the case of the bases with TiN.

FIG. 12 is an example of a graph showing the relationship between thewiring thickness for each base material and the sheet resistance ofwiring. FIG. 12 is a case of a wiring of 100 nm in thickness. Inaddition, FIG. 12 shows: (i) a case without a base; (ii) a case of usinga base of 5 nm thick TiN; (iii) a case of using a base of 5 nm WN; and(iv) a case of using a base of 10 nm thick WN. In each case, the wiringis formed from a film of W.

When the wiring is 100 nm in thickness, as shown in FIG. 12, the sheetresistance Rs of the wiring is not largely dependent on the wiringwidth, and the sheet resistance in the case of the base without TiN hasa value on the order of twice as large as the sheet resistance in thecase of the base with TiN. As described above, it is determined that thewiring resistance varies widely depending on the base material on whichthe wiring is deposited, even when the same wiring material is used.

The foregoing is applied to the upper wiring layer 114 (bit line BL)produced in accordance with the steps shown in FIGS. 5 to 10. When TiNis used as the material of the electrode EL3, the first section 114 a′deposited on the memory cell layer 110′ is smaller in crystal grain sizethan the second section 114 b′ of SiO₂ as a material. More specifically,it is determined that the sheet resistance of the first section 114 a′is larger in resistance value than the sheet resistance of the secondsection 114 b′. Thus, as long as the upper wiring layer 114′ isdeposited so that the proportion of the second section 114 b′ is higherthan that of the first section 114 a′, the wiring resistance of the bitline BL can be kept low.

Therefore, in the present embodiment, the proportions of the firstsection 114 a′ and second section 114 b′ of the upper wiring 114 areadjusted by adjusting the levels of the upper surfaces of the memorycell layer 110′ and interlayer insulating film 113′.

FIGS. 13 through 15A and 15B are cross-sectional views of a memory cellarrays for explaining differences in crystal grain size of wiring in thesemiconductor memory device according to the present embodiment.

In the case of the producing method according to the present embodiment,the upper wiring layer 114′ is deposited by using, for example, asputtering method as shown in FIG. 9. In this case, due to the nature ofthe sputtering method, the growth rate is quicker as the upper surfaceof the base is raised in position. Therefore, the first section 114 a′and second section 114 b′ of the upper wiring layer 114′ arespecifically as follows.

FIG. 13 shows a case of depositing the upper wiring layer 114′ afterleveling the upper surface of the memory cell layer 110′ and the uppersurface of the interlayer insulating film 113′. In this case, the firstsection 114 a′ grown from the upper surface of the memory cell layer110′ and the second section 114 b′ grown from the upper surface of theinterlayer insulating film 113′ are approximately comparable in growthrate, and the first section 114 a′ and the second section 114 b′ arethus both substantially quadrilateral.

On the other hand, FIG. 14A shows a case of depositing the upper wiringlayer 114′ after lowering (concaving) the upper surface of theinterlayer insulating film 113′ with respect to the upper surface of thememory cell layer 110′. In this case, the growth rate of the firstsection 114 a′ grown from the upper surface of the memory cell layer110′ is quicker than that of the second section 114 b′ grown from theupper surface of the interlayer insulating film layer 113′. Then, thefirst section 114 a′ is thus grown radially from the upper surface ofthe memory cell layer 110′, whereas the growth of the second section 114b′ is suppressed by the first section 114 a′ at the quicker growth rate.Therefore, the cross section with the row direction of the secondsection 114 b′ as a surface normal is shaped to have a smaller width inthe column direction on the upper side. As a result, the upper wiringlayer 114′ is deposited in which the proportion of the first section 114a′ is higher as compared with the second section 114 b′.

Furthermore, as shown in FIG. 14B, the use of a sputtering method formsthe upper wiring layer 114′ also from the side surfaces of the layer109′ located above the interlayer insulating film layer 113′ in somecases. While the upper wiring layer 114′ is also grown from theinterlayer insulating film layer 113′, the first section 114 a′ grownfrom the side surfaces of the layer 109′ blocks the growth above theinterlayer insulating film layer 113′. As a result, the growth of thesecond section 114 b′ is suppressed, and the upper wiring layer 114′ isdeposited in which the proportion of the first section 114 a′ is higheras compared with the second section 114 b′. In addition, the firstsection 114 a has a curved lower surface.

Furthermore, FIG. 15A shows a case of depositing the upper wiring layer114′ after lowering (concaving) the upper surface of the memory celllayer 110′ with respect to the upper surface of the interlayerinsulating film 113′. In this case, the growth rate of the secondsection 114 b′ grown from the upper surface of the interlayer insulatingfilm 113′ is quicker than that of the first section 114 a′ grown fromthe upper surface of the memory cell layer 110′, and the second section114 b′ is thus grown radially from the upper surface of the interlayerinsulating film 113′, whereas the growth of the first section 114 a′ issuppressed by the second section 114 b′ at the quicker growth rate.Therefore, the cross section with the row direction of the secondsection 114 b′ as a surface normal is shaped to have a smaller width inthe column direction on the upper side. As a result, the upper wiringlayer 114′ is deposited in which the proportion of the second section114 b′ is higher as compared with the first section 114 a′.

Furthermore, as shown in FIG. 15B, the use of a sputtering method formsthe upper wiring layer 114′ also from the side surfaces of theinterlayer insulating film layer 113′ located above the memory celllayer 110′ in some cases. While the upper wiring layer 114′ is alsogrown from the memory cell layer 110′, the second section 114 b′ grownfrom the side surfaces of the interlayer insulating film layer 113′blocks the growth above the memory cell layer 110′. As a result, thegrowth of the first section 114 a′ is suppressed, and the upper wiringlayer 114′ is deposited in which the proportion of the second section114 b′ is higher as compared with the first section 114 a′. In addition,the second section 114 b has a curved lower surface.

FIG. 16 is a graph showing the relationship between the depth of theupper surface of a memory cell layer to the upper surface of aninterlayer insulating film and the sheet resistance of wiring in thesemiconductor memory device according to the present embodiment. FIG. 16shows a case of using TiN as the material of the electrode EL3 in thememory cell MC, and using SiO₂ as the material of the interlayerinsulating film.

In this case, as described with reference of FIGS. 11 and 12, the firstsection 114 a′ undergoes a decrease in crystal grain size and anincrease in sheet resistance by the influence of TiN contained in thebase as the material of the electrode EL3. On the other hand, the secondsection 114 b′ undergoes an increase in crystal grain size and adecrease in sheet resistance, because no TiN is contained in the base.As a result, as shown in the graph in FIG. 16, the sheet resistance Rsof the entire bit line BL is decreased as the proportion of the secondsection 114 b with a lower sheet resistance is increased, that is, asthe depth α of the upper surface of the memory cell layer 110 isincreased with respect to the upper surface of the interlayer insulatingfilm 113. At this point, it is not limited the material of the electrodeEL3 is TiN. It is possible to use other materials as long as the crystalgrain size formed above the electrode EL3 is small.

In that regard, according to the steps of producing the memory cellarray 1 as shown in FIGS. 5 to 10, the wiring resistance of the bit lineBL can be reduced, because the upper surface of the memory cell layer110′ is made lower (concaved) than the upper surface of the interlayerinsulating film 113′ as shown in FIG. 17.

It is to be noted that the sheet resistance of the second section 114 b′is higher than the sheet resistance of the first section 114 a′ in somecases, depending on the materials of the memory cell layer 110′ andinterlayer insulating film 113′. In this case, as shown in FIGS. 14A and143, the wiring resistance of the bit line BL can be reduced by making(concaving) the upper surface of the interlayer insulating film 113′lower than the upper surface of the memory cell layer 110′.

In addition, when the sheet resistance of the first section 114 a′ iscomparable to the sheet resistance of the second section 114 b′, thewiring resistance of the bit line BL is not changed even in any case ofthe relationship between the memory cell layer 110′ and the interlayerinsulating film 113′ in terms of the level of the upper surface.However, as shown in FIGS. 13A and 13B, in the case of leveling thesupper surfaces of the memory cell layer 110′ and interlayer insulatingfilm 113′, there is no need to adjust the level of the upper surface ofthe memory cell layer 110′ or the interlayer insulating film 113′, andthe production process can be further simplified accordingly.

It is to be noted that when the upper surface of the memory cell layer110′ is made excessively deep with respect to the upper surface of theinterlayer insulating film 113′, or when the upper surface of theinterlayer insulating film 113′ is made excessively deep with respect tothe upper surface of the memory cell layer 110′, voids may be producedin dotted circles as shown in FIGS. 14A, 14B, 15A, and 15B.

Thus, according to the present invention, the proper adjustment made tothe levels of the upper surface of the memory cell layer and interlayerinsulating film can provide a semiconductor memory device that is low inwiring resistance and low in power consumption, and a production methodof the device.

Second Embodiment

In the second embodiment, Steps for removing an upper portion of amemory cell layer will be listed. The steps described herein may bereplaced with the step shown in FIG. 8 in the first embodiment.Therefore, the steps other than the steps described herein are the sameas in the first embodiment, and descriptions thereof will be thusomitted in the present embodiment.

FIGS. 17 to 19 are examples of perspective views illustrating steps ofproducing the memory cell array in the semiconductor memory deviceaccording to the present embodiment.

The first of the steps involves a method with the use of a dry etchingmethod. As shown in FIG. 17, the layer 109′ to serve as the topelectrode ELT of the memory cell MC is removed about 5 nm to 10 nm withthe use of a dry etching method.

The second thereof involves a method with the use of an ashing method.As shown in FIG. 18, a surface layer (shaded portions in FIG. 18) of thelayer 109″ to serve as the top electrode ELT of the memory cell MC isoxidized with the use of an ashing method. Thereafter, the layer 109″with W oxidized to WO_(x) is removed with the use of a wet etchingmethod. The wet etching can be carried out with the use of an alkalinechemical such as choline, which can selectively remove the surface layersection of the oxidized layer 109″.

The third thereof involves a method with the use of CMP. In planarizingthe upper surfaces of the memory cell layer 110″ and interlayerinsulating film 113″ by CMP, the upper surface of the layer 109″ toserve as the top electrode ELT can be lower (concaved) about 5 nm to 10nm as shown in FIG. 19 by slightly increasing the etching rate for thelayer 109″.

While the three methods for the step of removing an upper portion of thememory cell layer have been described above in the present embodiment,the adjustment made to the upper surfaces of the memory cell layer andinterlayer insulating film is not limited to these three methods, andcarious methods can be used. In any case, the proper adjustment made tothe upper surface of the memory cell layer and interlayer insulatingfilm before the deposition of the upper wiring layer can provide asemiconductor memory device that is low in wiring resistance and low inpower consumption, and a production method of the device, as in thefirst embodiment.

Others

While the several embodiments of the present invention have beendescribed above, these embodiments are presented by way of example, butnot intended to limit the scope of the invention. These novelembodiments can be implemented in other various embodiments, and variousomissions, substitutions, and changes can be made thereto, withoutdeparting from the spirit of the invention. These embodiments andmodifications thereof fall within the scope and spirit of the invention,and also fall within the invention as claimed in the claims andequivalents thereof.

What is claimed is:
 1. A method for producing a semiconductor memory device, the method comprising: when two directions crossing one another are referred to as a first direction and a second direction, whereas a direction crossing the first direction and the second direction is referred to as a vertical direction, forming a stacked body having a lower wiring layer formed on a semiconductor substrate, a memory cell layer formed on the lower wiring layer, and a plurality of interlayer insulating film dividing, in the first direction, the lower wiring layer and the memory cell layer into more than one section and extending in the second direction; removing an upper portion of the memory cell so that an upper surface of the memory cell layer is lower than an upper surface of the interlayer insulating film; and stacking an upper wiring layer on the memory cell layer and the interlayer insulating film.
 2. The production method of a semiconductor memory device according to claim 1, wherein a dry etching method is used in removing an upper portion of the memory cell layer.
 3. The production method of a semiconductor memory device according to claim 1, wherein a wet etching method is used in removing an upper portion of the memory cell layer.
 4. The production method of a semiconductor memory device according to claim 1, wherein CMP (Chemical Mechanical Polishing) is used in removing an upper portion of the memory cell layer.
 5. The production method of a semiconductor memory device according to claim 1, wherein an ashing method is used to alter an upper portion of the memory cell layer, before removing an upper portion of the memory cell layer.
 6. The production method of a semiconductor memory device according to claim 1, wherein an upper electrode layer in contact with the upper wiring layer is stacked as a portion of the memory cell layer in forming the stacked body.
 7. The production method of a semiconductor memory device according to claim 6, wherein the upper electrode comprises titanium nitride (TiN), the interlayer insulating film comprises a silicon oxide (SiO₂), and the upper wiring comprises tungsten (W).
 8. The production method of a semiconductor memory device according to claim 1, wherein the upper wiring layer is stacked so that a growth rate on the interlayer insulating film is quicker than a growth rate on the memory cell layer, in stacking the upper wiring layer.
 9. The production method of a semiconductor memory device according to claim 1, wherein in forming the stacked body, the lower wiring layer is stacked on the semiconductor substrate, the memory cell layer is stacked on the lower wiring layer, a plurality of first grooves extending in the first direction is formed in the memory cell layer and the lower wiring layer, and the first grooves are filled with the interlayer insulating film. 